The DFFREG component is an edge-triggered digital flip-flop register with an active-high reset and a configurable output delay. A positive transition (1-Trns) of the clock causes the input data to be latched and appear at the output after the specified delay.
The strength parameter specifies a map on logic signals. Its value consists of a symbol, , with being one of the following: . The three subscripts define the map:
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A U always maps to a U.
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{X,Y,W,-} map to the first subscript ().
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{0,L} map to the second subscript ().
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{1,H} map to the third subscript (h).
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For example, means {X,Y,W,-} map to X, {0,L} map to 0, {1,H} map to H.
DataIn
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Clock
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Reset
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DataOut
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*
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*
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U
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U
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*
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*
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1
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0
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*
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0-Trns
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0
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NC
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*
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1-Trns
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0
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DataIn
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*
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X-Trns
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0
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X or U or NC
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*
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*
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X
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X or U or 0 or NC
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Symbol Definitions
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Symbol
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Definition
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Clock Transition Definitions
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Symbol
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Definition
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1-Trns
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0-Trns
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X-Trns
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